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Noise_Design-Oriented Estimation of Thermal Noise in swtich cap circuit_图文

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 11, NOVEMBER 2005

Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits
Richard Schreier, Member, IEEE, José Silva, Member, IEEE, Jesper Steensgaard, Member, IEEE, and Gabor C. Temes, Life Fellow, IEEE

Abstract—Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) ?lters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II–III). It also proposes some specialized but highly ef?cient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV–VI). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is veri?ed by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter. Index Terms—Delta-sigma itor (SC) circuit, thermal noise.

drain current. If the transistor operates in its triode region, as it does for a conducting switch, the noise can be represented by a voltage source in series with the device. The power spectral density (PSD) of its voltage is white; its estimated value is given by (V Hz (1)

(16) modulator, switched-capac-

Here, is the Boltzmann constant, J/K, is the absolute temperature of the device in degrees Kelvin, and is its on-resistance in ohms. The mean value of the thermal noise is zero. Note that here, and in the rest of this paper, all PSDs are regarded as one-sided distributions, so the noise power between and is obtained simply by integrating between and . For a MOSFET operating in strong inversion and in its active region, the thermal noise can be modeled by a current source in parallel with the channel. The PSD of the noise current is to a good approximation given by (A Hz (2)

I. INTRODUCTION

O

NE of the main limitations of the performance of switched-capacitor (SC) circuits is noise. The sources of noise include the intrinsic noise generated in the MOS transistors, as well as the extrinsic (interference) noise originating, typically, from the on-chip digital circuitry, and coupled into the sensitive analog stages via the substrate and supply or ground lines. There are two important intrinsic noise effects in MOS transistors: thermal and ?icker noise1. Thermal noise is caused by the thermal motion of the charge carriers in the channel of the device. This causes a small amount of random ?uctuation in the
Manuscript received October 28, 2004; revised February 23, 2005. This work was supported in part by the NSF Center for the Design of Analog and Digital Integrated Circuits (CDADIC). This paper was recommended by Associate Editor A. Baschirotto. R. Schreier and J. Silva are with Analog Devices, Inc., Wilmington, MA 01887 USA (e-mail: richard.schreier@analog.com; jose-b.silva@analog.com). J. Steensgaard is with ESION LLC, Carlsbad, CA 92018 USA (e-mail: steensgaard@ieee.org). G. C. Temes is with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA (e-mail: temes@eecs.oregonstate.edu). Digital Object Identi?er 10.1109/TCSI.2005.853909

is the transconductance of the device. where Flicker noise or noise is caused by charge carriers getting trapped and later released as they move in the channel. It is usually modeled by a series noise voltage source connected to the gate. The PSD of this voltage is approximately given by (V Hz (3)

1Shot noise, which is due to the random ?ow of discrete charges under high electric ?eld conditions, is signi?cant mostly in the forward-biased p-n junctions, which do not exist in common MOS devices. It may occur, however, in deep submicron devices if signi?cant gate current ?ows.

where and are the width and length of the channel, is the frequency, and is a fabrication parameter. Note that is not white; most of its power is concentrated at low frequencies. The reader is referred to the many available texts (e.g., [1, ch. 4]) for a more detailed discussion of intrinsic device noise. noise may be reduced using In many cases, the effects of large input devices, and choosing them as pMOS rather than nMOS transistors. Also, correlated double sampling or chopper noise, or stabilization [1], [2] may be used to suppress the to modulate it to out-of-band frequencies. In this paper, the effects of thermal noise on the performance of SC circuits will be discussed, and an ef?cient algorithm will be described for estimating the magnitude of these effects. Section II considers the noise effects in the CMOS operational ampli?ers (op-amps) commonly used in SC circuits. Section III contains a general analysis of ?ltered and sampled thermal noise. Section IV describes an algorithm for calculating the

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Fig. 2. Op-amp with capacitive feedback and capacitive loading.

Fig. 1. Noise sources in a simple CMOS op-amp.

input- and output-referred noise power generated in a SC integrator, and proposes a design technique based on it. Section V compares the noise performances of single-ended and differential structures; Section VI gives a numerical example of the estimation process for an integrator. Finally, Section VII describes the application of the estimation algorithm to a SC delta-sigma modulator. All derivations in this paper assume that the output of the SC circuit is being sampled, and hence, only the discrete-time output noise is of interest. In some applications (e.g., in the analysis of the reconstruction ?lter of a delta-sigma digital-toanalog converter), the continuous-time output noise must be found. This noise contains a component directly fed from the noise sources to the output with an essentially white spectrum, as well as a sampled-and-held one. Both spectra represent continuous-time signals, and hence, they are not periodic. By contrast, based on physical considerations to be discussed in Section III, all sampled noises considered in this paper will have periodic spectra. The discussions in this paper do not extend to the analysis of continuous-time noise; the reader may consult the available literature, e.g., [3], [9] for an analysis of this condition. More detailed discussion of some issues mentioned in this paper can be found in [4] and [5]. II. THERMAL NOISE EFFECTS IN CMOS OP AMPS Next, the estimation of thermal noise in op-amps will be discussed. As an illustration, a differential pair (which may be the input stage of a multistage op-amp) is shown in Fig. 1, along with its thermal noise current sources. These represent the effect of the noise currents, given in (2). It can readily be seen that the noise current of the tail device Q5 does not contribute to the output current, since it is present in the drain currents of both Q2 and Q4, and hence, cancels in the output current under ideal matching conditions. (This is a good approximation only at frequencies where the gains and delays of the two paths match.2) The noise currents of the input devices (assumed to be perfectly matched) can be represented by equivalent noise voltage sources at their gate terminals. From (2), the PSDs of these sources are . The noise current of Q3 can also be repgiven by resented by a voltage source at the gate of Q1. The PSD of this . Similar considerations hold when source is
2More

the noise of Q4 is represented by an equivalent source at the input of Q2. Combining these results, the total thermal noise of the stage may be represented by a single equivalent noise voltage source at the gate of Q1 (or Q2). Its PSD is (4) The ?rst equality of (4) suggests that for low noise should be used, which justi?es the approximation made in the last part. Consider next the op-amp under negative feedback conditions (Fig. 2). Note that the op-amp noise is represented by the , and that no signal is present since only equivalent source the noise ampli?cation is analyzed. It will be realistically assumed that the op-amp is properly compensated, so that in the frequency range of interest (where the loop gain is 1 or larger) the closed-loop transfer function can be approximated by the one-pole expression (5) Here, is the dc gain of the stage, and is its settling time conis determined by the feedback factor stant. and by the dc gain of the op-amp. Assuming , we ?nd (6) Since the settling time is determined by how fast the op-amp output current can charge the load capacitances, will be proportional to . Also, since feedback reduces , it may be , where depends on written in the form the structure of the op-amp. For a two-stage op-amp, , where is the compensation capacitance connected between the stages ([1, ch. 5]). For a single-stage (folded- or teleis the load capacitance at the output scopic-cascode) op-amp, . node of the op-amp: The PSD of the white input noise becomes shaped at the output by the ?rst-order low-pass ?lter function given in (5). The mean-square (MS) value of the output noise may be calculated by integrating the shaped PSD from dc to in?nite frequency (7) Substituting the values derived above for and gives (8)

importantly, it is a good approximation in fully differential circuits.

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Fig. 3.

Noise signals in a sampled system.

The MS value of the output noise voltage for unity-gain feedin back can also be obtained, simply by setting (8) (9) Notice that even though the PSD of the op-amp’s input noise source is determined by , (8) and (9), which give the MS . This is because value of its output noise, do not contain , while the bandwidth the PSD is inversely proportional to of the stage is directly proportional to it. Hence, its effect cancels in the calculation of the MS output noise. III. SAMPLED THERMAL NOISE The discussions of (5)–(7) can easily be generalized, and extended to sampled noise. As shown, when a thermal noise with a white spectrum is processed by a voltage ?rst-order ?lter with a transfer function

Fig. 4.

A stray-insensitive SC integrator.

will be very the spectrum of the sampled noise signal nearly white3. The aliasing described above increases the PSD of the noise resigni?cantly. The MS value of the sampled signal , since all its samples are taken mains the same as that of . Since is a (nearly) from synchronous values of white noise, its PSD can be found from (14) Since the low-frequency PSD of is , the PSD has , which by (12) is larger than increased by a factor . For example, if bits, the noise PSD is magni?ed by a factor of 7.6, or 8.8 dB. This represents an inherent disadvantage of sampled-data analog signal processors, such as SC and switched-current ?lters, as compared to continuous-time ones. Note that in oversampled SCFs followed by a unity-gainpassband digital LPF, the MS value of the oversampled noise is reduced by the oversampling ratio OSR after digital ?ltering. IV. NOISE EFFECTS IN AN SC INTEGRATOR

(10) the result is a noise voltage PSD has a 3-dB bandwidth at MS value with a low-pass spectrum. Its , and it has a dB

(11) The time constant determines the required settling time of the response. system, since its transient follows the Assume next that the thermal noise source feeds a low-pass ?lter (active or passive) whose voltage output is sampled on a capacitor (Fig. 3), at a clock rate . Let the continuous-time from to , when is connected transfer function to the ?lter, be given by (10). If the system must have an -bit performance, then the settling error at the output of the LPF must be less than half an LSB. For a 2-phase system, this requires that the condition (12) or equivalently dB

Consider next the stray-insensitive SC integrator shown in Fig. 4. As indicated, the sampling instants are at the end of the clock phases. For ideal components, the tracks the input voltage voltage across the input capacitor when is high, and stores a charge at the end of the phase. During discharges into the virtual ground created by the op-amp. This causes the charge at the end of to become stored in (15) Hence, the output voltage satis?es (16) Next, we consider the noise contributed by the switches through (Fig. 5). The only signi?cant noise effect introduced

(13)
3Another possible explanation for this phenomenon is that under conditions (12)–(13) the memory span of the LPF is much shorter than 1=f . Hence, the samples of v (t) taken at times n=f ; n = 1; 2; . . . are very nearly uncorrelated. This property results in a white spectrum for v (n).

bits, then (13) requires be satis?ed. For example, if . Thus, the PSD of the block output that dB will be heavily aliased in the sampling process. Due to folding,

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Fig. 6. Fig. 5. Noise analysis for the integrator in Fig. 4.

Noise analysis for a single-stage ampli?er.

by these switches is thermal noise4. For simplicity, will across be assumed. We shall ?rst ?nd the noise voltage due to the thermal noises generated in switches and . is high, the circuit containing can be represented While by the branch shown in Fig. 5(a). Here, the conducting switches and have been replaced by their noise voltages and on-resistances. As illustrated in Fig. 5(b), the noise voltages and resistors can be pairwise combined. Assuming that all , the combined switch resistance is switches have the same and (since and are uncorrelated) the PSD of the associated noise voltage is . across can be expressed The PSD of the noise voltage as follows: in terms of the PSD of (17) where is the time constant of the branch . has a low-pass-?ltered spectrum; it is during , while its 3-dB (halfno longer white. Its dc value is power) frequency is . can be obThe total power (mean-square value) of for all frequencies from 0 to intained by integrating ?nity. This gives (18) . The explanation is that the dc which is independent of , while its bandwidth value of the PSD is proportional to 5. The noise charge stored in is proportional to is ; its mean-square value is . period (i.e., at ), switches At the end of the th and will open, and the charge is trapped in . has the same mean-square The sequence value as , since it is constructed from the samples of . However, due to the sampling, the PSD of is nearly
the current ?ow in these switches consists of short pulses occurring at the clock rate, the 1=f noise (which is caused by the trapping and release of charge carriers occurring at long intervals) has only a negligible effect here. 5An alternative derivation appeals to the physical principle known as Equipartition of Energy, which states that the average energy associated with any degree of freedom in a system at thermal equilibrium is kT =2. For a capacitor C  charged to a voltage v , the electrical energy is E = Cv =2 and thus, E = kT =2 implies v = kT =C .
4Since

perfectly white. The reason for this is aliasing, as discussed in . Section III, since (13) must hold here for rises, switches and close. The resulting Next, when noisy circuit is shown in Fig. 5(c). To make the analysis more speci?c, we shall assume a single-stage op-amp6 represented by the model shown in Fig. 6(a), compensated by its capacitive load. The diagram of Fig. 6(b) illustrates the resulting ciris high. Note that the on-resiscuit during the time when tances and noise voltages of the two switches have again been combined. In the analysis of the circuit, it is reasonable to assume that , the loop gain of the stage satis?es the condition ; this is necessary for suppressing where signal distortion caused by op-amp nonlinearity. Under this may be assumed, and the calculation condition, simpli?ed. may Using the Laplace transform, the noise voltage across be found as (19) where (20) Utilizing the results of Section III, the MS value of the can be calculated voltage due to the switch noise noise

(21) Here, the parameter The noise power in was introduced. due to op-amp noise can also be found

(22) Consider next the total noise power stored in . At the end had acquired of clock phase , as illustrated in Fig. 5(b), whose power was given by (18). During a noise voltage , the noise voltage becomes . The phase
6The single-stage op-amp is the most commonly used active element in SC integrators, and it allows the simplest treatment of the noise issue. Two-stage ampli?ers can be analyzed similarly, but require a more elaborate analysis, and are not discussed in this paper.

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of noise from the op-amp is due to the fact that [as (4) shows] the input-referred noise of the op-amp is inversely proportional . to For a given capacitor size (i.e., for a ?xed ), the condition yields the minimum achievable noise. For a circuit whose area is dominated by its capacitors, this condition corresponds to the minimum-area solution. However, since realizing a large requires a large current, the most power-ef?cient value of subject to constraints solution is the one that minimizes on the noise power [cf. (23)] and the settling time [cf. (20)]. Combining these relations leads to
Fig. 7. Relative contributions from the switches and op-amp to the total integrator thermal noise.

(24) which is clearly minimized for . Since, according to (23), the total noise power associated with this solution is , the size of in the minimum-power design is only about 17% larger than the size of in the minimum-capacitance design. at the From (23), the mean-square noise charge stored in phase is given by end of the (25) during Consider next the noise charge delivered to . arrives at the virtual ground carrying a charge . , Since the time constant of the stage is much shorter than phase, and will be this charge will disappear by the end of the replaced by . Since all voltages are uncorrewill lated, the change in the MS value of the noise charge in and be the sum of the MS charges due to voltages , as given by (25). Since and become series-connected as rises, acquires the same additional noise charge is , and as . Hence, the added noise charge for is increased by the MS noise voltage of (26) clock phase. during each It is often useful to represent the effect of the accumulated noise contribution from a stage by one or more equivalent voltage sources at the input and/or output of an otherwise ideal and noiseless circuit. As discussed above, the effect of thermal noise in the transistors of the switches and the op-amp in a SC and , with an integrator is an added noise charge in both MS value given in (25). In a noiseless and ideal SC integrator, by connecting an equivthis charge can be delivered into to the input of the integrator. alent noise voltage source is the same as that of , given in (23); The MS value of is a sampled-data signal with a white spectrum. Frequently, there are several SC input branches in an in, the tegrator. Assuming for simplicity that total noise charge contributed by the switched input capacitors to is given by (27)

components have the noise powers given in (21) and (22). The during is hence, . change in Since the three noise voltages are uncorrelated, their powers are added. Hence, the total noise power is7

(23) As (20)–(22) show, the ratio of the switch noise power to the op-amp noise power generated during is . Thus, for (i.e., for ), the op-amp dominates both , the bandwidth and the noise, while for the switch effects dominate. The overall situation considering both clock phases is shown in Fig. 7. , if The total noise power is minimized, and becomes , i.e., if the condition holds. Under these conditions, all noise is contributed by the switches. The absence
7Expressions (18), (21), and (22) represent the continuous-time dynamics of the voltage v (t), and (23) assumes that the corresponding charge distribution is ideally frozen in time at the end of the respective clock phases. In other words, the turn-off transition of the switches is assumed to be ideal. Several nonidealities associated with the turn-off transition of real world MOSFET-based switches, however, may affect the circuit’s noise properties. ? Finite transition time of the switches’ control signals will cause a gradual transition of their impedance from R to R . If this effect becomes pronounced, the effective value of x may be higher than x = 2R g . ? MOSFET-based switches store charge in the conductive channel when they are turned on. This inversion charge is released when the switch is turned off. The distribution of the released charge carriers to the two switch terminals is to some (unknown) extent a stochastic process. Expression (23) does not account for this noise contribution. The error is believed to be negligible in many cases, but the reader is cautioned that (21) may underestimate the sampled noise from the switches for small values of x (the inversion charge is proportional to 1=R ). A conservative circuit designer may choose to replace (21) by kT =C , which is an upper limit for the switches’ (S and S ) total sampled noise contribution. Note also that the derivation of (18) is based on the assumption that the settling time constant is given by  = 2R C , i.e., it is assumed that the signal source driving C has an arbitrarily high bandwidth. If the bandwidth is effectively limited by the signal source rather than R , the effective noise contribution from S and S may be less than kT =C . In that case, (18) should be replaced by an expression similar to (21). However, considering the uncertainty pertaining to the nonidealities associated with the switches’ turn-off transition, the conservative circuit designer may choose to use the upper limit 2kT =C for the total switch-induced noise power in C .

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V. SINGLE-ENDED VERSUS DIFFERENTIAL CIRCUITS
Fig. 8. Equivalent noise sources for the integrator of Fig. 4.

Thus, a large input capacitor contributes more noise than a small one does. In the typical case where , we may use . (25) and (26) by substituting In the input stage of a SC delta-sigma loop, it is possible to use either a single capacitor to enter both input and DAC signals, or to use two separate ones. As (27) demonstrates, the latter solution introduces up to twice as much thermal noise power as the ?rst one, so the SNR is reduced by up to 3 dB. Using only one capacitor, however, may cause signal-dependent disturbances in the DAC reference voltage, which is another important aspect to consider in the design. models the noise The input-referred noise source charge entering in every clock period, and hence the noise . However, the output voltage is the sum of and voltage at the inverting input terminal of the op-amp the voltage , when the output voltage is sampled, [Fig. 5(c)]. During the circuit is in a unity-gain con?guration (in small-signal may be obtained from (9). Since sense), and the MS value of is added only to the output voltage, it may be represented by . an output-referred sampled-data voltage source The MS value of is given by (9); for the op-amp represhould be used (Fig. 4). The sentation of Fig. 6(a), overall model of thermal noise effects is shown in Fig. 8, where the center box represents an ideal noiseless SC integrator. As will be illustrated in the example given below, the efis usually negligible compared to that of . fect of Hence, the relative contributions of the switches and the op-amp to the integrator noise can be predicted from (23), as functions . The resulting curves are shown in Fig. 7. As of the curves illustrate, the noise due to the op-amp is comparable to the noise due to the switches when is small, but when is large the switch noise dominates. Next, the use of the above estimation results in the design of the integrator will be discussed. As (24) shows, the MS value increases with , and it is inversely proportional to and of . Hence, it is expedient to choose , and to make as large as (12) allows, i.e., to choose (28) If, for example, chosen. Then, gives bits, then can be found from (24). For should be , this

The described noise calculations assume single-ended circuit con?gurations. We will now estimate and compare the noise performance of a fully differential circuit based on the same total . To preserve the total capacitance, capaccapacitance and are each split in two equal parts, and the two itors halves are assigned respectively to the positive and the negative side of the differential circuit. To enable a fair comparison of the noise properties of singleended versus differential circuits, we must ?rst determine the key properties characterizing the opamps driving the respective capacitor con?gurations. We will use the single-ended transconductance ampli?er (opamp) shown in Fig. 1 as a vehicle for this is divided equally beanalysis. The opamp’s input signal tween the two input transistors, Q1 and Q2, producing the drain . The current mirror (Q3 and Q4) currents will invert the current , and the single-ended opamp will thus produce the output current (31) In an equivalent fully differential opamp, the gate terminals of Q3 and Q4 will be driven by a common-mode feedback circuit, and the two output currents will simply be the drain currents of Q1 and Q2 (32) To facilitate the noise analysis, we have to determine for each (of Q1 and Q2) needed type of circuit the transconductance to make the respective circuits settle with the appropriate time . The required constant (12): values differ for the two types of circuit. For simplicity and without loss of generality, we will assume that the ?ve transistors have prede?ned aspect ratios, and that they for the all contain unit devices with the same multiplicity: single-ended opamp and for the differential opamp. The of the opamps are thus respeceffective transconductances and , where is the transconductance tively of each unit-sized transistor used to implement Q1 and Q2. The topology and the main features of the circuits are shown in Fig. 9. The single-ended circuit will settle with the time constant . Using the concept of half circuits, and may each be split into two halves, and we ?nd that the differential circuit will settle with the time constant . Notice that, when compared to the singleended circuit, each half of the differential circuit has the same , and that it (for ) effective transconductance will settle twice as fast, because it is subject to only half the capacitive load. In practice, however, the circuits should be designed to settle with the same time constant8, which implies that .
8In reality, the capacitive load is not reduced exactly by a factor of two, because the differential opamp’s input capacitance is larger than that of the single-ended opamp. Speci?cally, if C denotes the gate-source capacitance of one unit transistor, the differential opamp’s input capacitance is M C (half circuit), and the single-ended opamp’s input capacitance is (M =2) C . When taking this difference into account, we may calculate the )=M g and  = settling time constants as  = (C + 0:5M C C )=M g = (C + 2M C )=2M g . (0:5C + M Equivalent settling properties are, therefore, achieved when M = (M C =2C )) . (M =2)(1

(29) is again determined by where the permissible MS value of and by the input signal level of the integrator. Finally, can be calculated from (29) and from (20), which may be rewritten in the form (30)

1

1

1

1

1

0

1

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Fig. 9. Topology and main properties of the single-ended and fully-differential circuits.

With the above results in place, we are now ready to compare the noise performances of the two types of circuits assuming the same total capacitance and settling time constant. The total noise of the single-ended circuit is given by (23). The differential circuit has more and larger noise sources. Because the capacitors are each half the size (and twice as many), we ?nd that the noise contribution corresponding to (18) is . Likewise, we ?nd that the noise contribution corre. Finally, we may calsponding to (21) is culate the noise contribution corresponding to (22) by adding the noise contributions from the two half circuits9 (33) The total input-referred noise [corresponding to (23)] for the differential circuit is thus

(34) We can calculate the ratio of the differential circuit’s noise level to that of the single-ended circuit from (35) At ?rst sight it may be disappointing that the differential circuit has a relatively much higher (4.5 dB) noise ?oor, but the result should be evaluated in the proper context. The full-scale signal swing of the differential circuit is twice that of the single-ended circuit, and hence, the dynamic range of the differential cirdB dB higher than that of the cuit is about dB single-ended circuit. Furthermore, it is important to remember that the imposed requirement of equivalent settling behavior im, i.e., the fully-differential circuit conplied that sumes only half as much power as the single-ended one does. Now consider a comparison where the power consumption and the time constants are assumed to be equal. The differential circuit will drive twice as much capacitance as the single-ended
(kT =C

circuit. This will improve the dynamic range of the differential circuit by an extra 3 dB, which makes the dynamic range advantage a full 4.5 dB. Typically, a given application will require the circuit to have a speci?ed dynamic range. If we make a comparison where the dynamic ranges and the time constants are equal, we ?nd that % of the differential circuit will consume only the power required by the single-ended circuit. Fully differential circuits are thus preferable not only because they suppress evenorder harmonic distortion and are more robust to extrinsic noise, but also because they allow a longer battery life and/or smaller chip size. The above results have been veri?ed by means of simulations. A cascoded version of the considered simple ampli?er strucand ture (Fig. 1) was designed and simulated for . The corresponding current consumptions were, respectively, 30 A and 15 A, and the opamps were driving capF. The unit-sized input transistors each pacitive loads S. The observed/simuhad a transconductance of lated time constants were, respectively, 44.6 and 46.0 ns, which is within a few percent of the values anticipated by our analysis. The input-referred noise from the opamps was, respectively, (12.2 nV) /Hz and (17.4 nV) /Hz, which is about 51% higher (power) than the anticipated values. This discrepancy is not a cause of concern, since the additional noise can be tracked back to Q3 and Q4 (and the increase is approximately the same for both the single-ended and the differential circuit). Overall, we ?nd that the noise power of the single-ended circuit is (for ) nV Hz V (36) pF ns and that the total noise of the differential circuit is nV Hz V (37) pF ns which implies that the dynamic range of the differential circuit is approximately 1.8 dB better than that of the single-ended circuit. This is remarkable in itself, but more so when taking into account that the differential circuit uses only half the power. Finally, it should be noted that the noise estimation process discussed here remains a good approximation up to a radian , even if the op-amp model includes frequency in parallel with (Fig. 6). an output capacitance VI. INTEGRATOR NOISE ANALYSIS EXAMPLE The following example illustrates how to calculate the output noise for the integrator shown in Fig. 4, given some speci?c values. MHz. It is assumed that the clock frequency is The signals must settle to an accuracy of bits, and V is desired. The an input-referred noise voltage , and must drive integrator has a gain factor pF during phase . To ensure the load capacitance that the op-amp dominates bandwidth and noise, was selected. These speci?cations are used next to calculate the circuit parameters according to (28)–(30). The settling time constant is ns, and thus 7.6 times smaller than the determined as

that the opamp’s contribution for each half circuit, (4=3) 1 ' 0 is less than (kT =C =2) = (2kT =C ), which is not surprising considering that the input-referred noise of a MOSFET, (2=3) 1 (4kT =g ), is less than the noise of a resistor having the same conductance g .
9Note

=(1 + x)), for x

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settling period of ns. The ampli?er is an OTA with mA/V. For simplicity, to make transconductance , the output impedance is assumed to be the dc gain k . The input capacitance is then calculated as pF, and pF. The switches must . have an on-resistance The PSD of the output-referred noise is given by (38) In this equation, the power of the input-referred noise source is given by (23), while that of the output noise source is given by (9). is obtained by dividing the power of by . is the integrator transfer function. It can be In (38), found using available SC analysis programs, such as SWITCAP, or analytically, as shown below. For the integrator with a ?niteis given by [6] gain op-amp, (39) The parameter is the integrator gain factor, as de?ned above. Also, . The parameter in the input-referred . noise source is The output-referred noise power can be calculated by inte[given in (38)] in the signal band, grating the output PSD from 0 to . The resulting equation is very complicated, and tedious to calculate manually. Since both and are frequency-independent, only needs to be integrated. This can be done simply numerically, using (39). Alternatively, the integration may be carried out analytically. A symbolic analysis tool, such as Maple [7], can be used for this calculation. The integrated noise power is then found to be

Fig. 10. Calculated and simulated integrated noise powers at the output of an integrator.

Fig. 11.

Noise sources in the feedforward topology.

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Fig. 12. Schematic of the feedforward topology.

The output noise power can also be simulated by a dedicated CAD tool, such as SpectreRF [8]. This circuit simulator has built-in analysis routines that can handle discrete-time circuits. Fig. 10 shows the calculated and simulated output noise powers, , as functions of . It also shows the noise contribution of which is negligible here for all values of shown, as predicted earlier. The good agreement between the calculated noise and the simulated one con?rms the usefulness of the theory discussed earlier. VII. THERMAL NOISE EFFECTS IN A DELTA-SIGMA LOOP As an example of the use of the described noise estimation algorithm, we shall next apply it to the design of a secondorder low-distortion delta-sigma modulator. Its block diagram blocks represent SC integrators is shown in Fig. 11; the using the circuit of Fig. 4. The complete circuit is shown in , Fig. 12. We shall assume an oversampling ratio dBV), and a maximum input signal power of 0.25 V ( a desired 13-bit performance (i.e., an SNR of 80.0 dB). The

total permissible noise power (including quantization error, exV . trinsic noise, etc.) is then Assigning 75% of the noise power to thermal noise [4], the total permissible input-referred thermal noise power turns out to be V . In addition, the quantizer resolution must be chosen such that the quantization noise power is a negligible portion of the total noise power. Assigning 10% of the total noise power to the shaped in-band quantization noise, we ?nd that a 5-bit quantizer is required for this structure. Since the signal transfer function for this structure is ideally , the output-referred noise power is the same as the input-referred one10.
10Here, for simplicity, we assume that the quantizer has a gain of 1. Note that this assumption effectively assigns a physical unit, say volts, to the digital output value. Note also that in the circuit diagram of Fig. 12, a capacitive voltage divider attenuates the input signal at the quantizer input by a factor of 4. This can be compensated for by using a quantizer gain with the same factor.

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To ?nd the minimum acceptable values of the switched input and of the two integrators, and of the input capacitors capacitors of the quantizer Q, the following steps need to be performed. 1) Identify the thermal noise sources (SC branches, op-amps) in the circuit: In this circuit, there are ?ve SC branches (Fig. 12): one is shared at the input of the ?rst integrator (note that between the input and feedback signal paths), one at the input of the second integrator, and three at the input of the quantizer. The latter are ratioed, so only one of them (say, connecting to the input of Q) may be selected arbitrarily. There are also two op-amps, one in each integrator. The corresponding noise sources are indicated in Fig. 11. 2) Find the PSDs of all noise sources: Since all noise sources are sampled, with white PSDs, for the th source the PSD may be found from the MS noise voltage simply as (41) The MS value of the input-referred noise voltage of the ?rst integrator is, by (23) (42) The noise source at the output of the ?rst integrator has the MS value [from (9)] (43) is the effective load capacitance of the op-amp where during clock phase , given by . The MS noise voltages at the input and output of the second integrator are given by expressions similar to (42) and (43). The noise contributions of the three SC branches at the input of Q can be combined to give a noise power

Fig. 13.

Frequency responses of the noise power transfer functions.

The NTF from the output of the ?rst integrator is (47) The NTF from the input of the second integrator is (48) Finally, the NTF from the input of the quantizer (and from the output of the second integrator) to the modulator output is (49) The corresponding frequency responses are shown in Fig. 13. 4) Integrate all noise PSDs, multiplied by the corresponding , from dc to the signal power transfer functions : band edge This may be performed numerically or analytically. If the latter procedure is followed, a symbolic analysis tool may be used. The resulting output noise powers turn out to be

(44) 3) Find the voltage and power transfer functions from each noise source to the output: This may be done numerically, using a dedicated SC analysis program, or analytically. We shall illustrate the latter method. Using (45) the noise voltage transfer function from the input of the ?rst integrator to the output of the modulator is found to be (46) (52) (50)

(51)

(53)

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These expressions can be considerably simpli?ed if a high , the output noise powers OSR is used. With become

(54) (55) (56) (57)

results for a typical SC integrator with those given by a state-ofthe-art CAD program. Based on the model, an optimum strategy was also suggested for the design of SC integrators incorporating thermal noise considerations. Finally, an example illustrated the use of the proposed estimation process in the design of a second-order delta-sigma modulator. ACKNOWLEDGMENT Useful discussions with P. Hanumolu are acknowledged, as well as the very helpful comments of the reviewers. REFERENCES

5) Add the noise powers due the individual noise sources to obtain the total output thermal noise; equate it to the permissible noise, and use this to ?nd the minimum values of the SC. into the expressions for and Substituting , and into the equations obtained in Step 4, the total output thermal noise power is

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Since the ?rst term dominates, the minimum value of can be obtained directly

[1] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997. [2] C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996. [3] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. New York: Wiley, 1986, sec. 7.4. [4] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. Piscataway, NJ: IEEE Press/Wiley, 2005. Appendix C. [5] J. Steensgaard, “Noise sources in switched-capacitor delta-sigma modulators,” in Lecture Notes for “Practical Approach to Delta-Sigma Design” EPFL/MEAD Microelectronics Short Course, Lausanne, Switzerland, Jun. 21–25, 2004, [Online]: Available http://www.steensgaard.org/jesper/publicat ions.htm#DSM_NOISE_2004_06_23. [6] W. Ki and G. C. Temes, “Offset-compensated switched-capacitor integrators,” in Proc. IEEE Int. Symp. Circuits and Systems, May 1990, pp. 2829–2832. [7] A. Heck, Introduction to Maple. New York: Springer-Verlag, 2003. [8] K. Kundert. Simulating switched-capacitor ?lters with Spectre RF. [Online]. Available: http://www.designers-guide.com/Analysis//sc-?lters.pdf [9] L. Toth, I. Yusim, and K. Suyama, “Noise analysis of ideal switched capacitor networks,” IEEE Trans. Circuits syst. I, Fundam. Theory Appl., vol. 46, no. 3, pp. xx–xx, Mar. 1999.

pF

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Richard Schreier (S’89–M’91) received the Ph.D. degree from the University of Toronto, Toronto, Canada, in 1991. He was a Professor with Oregon State University, Corvallis, from 1991 to 1997. He is with the High Speed Converters Group, Analog Devices, Wilmington, MA. He is the author of the freeware delta-sigma toolbox for MATLAB and coauthor (with G.C. Temes) of Understanding Delta-Sigma Data Converters (Piscataway, NJ: IEEE Press/Wiley, 2005). Dr. Schreier is a recipient of the 2002 ISSCC Best Paper Award.

The other SC may be chosen to be much smaller than

.

Note that, as indicated in Step 4, it is the high OSR which makes the output noise (almost) independent of all switched capacitances other than for this modulator. In general, a simple optimization can be performed to minimize the total capacitance for a desirable thermal noise level.

VIII. CONCLUSION The effects of thermal noise generated by the switches and op-amp devices in an SC circuit were analyzed. The analysis was simpli?ed by assuming that the circuit contains only ?rstorder blocks (SC branches, feedback op-amps), all designed to settle within half a clock period. This very practical assumption allowed a simple noise estimation process, resulting in a noise model consisting of input- and output-referred equivalent noise sources. The model was veri?ed by comparing the estimation
José Silva (S’98–M’04) received the diploma in electrical and computer engineering from the Instituto Superior Técnico (IST), Lisbon, Portugal, in 1994, and the Ph.D. degree from Oregon State University, Corvallis, in 2004. From 1993 to 1996, he was a Research Assistant with the Integrated Circuits and Systems Group, IST. In 1996 and 1997, he worked for Landis & Gyr, Zug, Switzerland. Since 2004, he has been with Analog Devices, Inc., Wilmington, MA.

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Jesper Steensgaard (S’96–M’99) received the M.S. and Ph.D. degrees from the Technical University of Denmark in 1994 and 1999, respectively. From 1996 to 1998, he was a visiting scholar with Oregon State University, Corvallis, and from 2000 to 2001, he was an Assistant Professor with Columbia University, New York. During 2001–2002, he worked as a senior scientist for Microsemi Inc, Carlsbad, CA. He is a founder of iCoustics LLC and ESION LLC, Carlsbad, CA. His research addresses the theory and design of delta-sigma data converters with low-power and wide-signal bandwidth.

Gabor C. Temes (SM’66–F’73–LF’98) received undergraduate degrees from the Technical University of Budapest and E?tv?s University, both in Budapest, Hungary, in 1952 and 1955, respectively. He received the Ph.D. degree in electrical engineering from the University of Ottawa, Ottawa, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest in 1991. He held academic positions at the Technical University of Budapest, Stanford University, Stanford, CA, and the University of California at Los Angeles (UCLA). He worked in industry at Northern Electric R&D Laboratories (now Bell-Northern Research), Ottawa, Canada, as well as at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science, Oregon State University (OSU), Corvallis. He served as Department Head at both UCLA and OSU. His recent research has dealt with CMOS analog integrated circuits, as well as data converters. He coedited and coauthored many books; the most recent one is Understanding Delta-Sigma Data Converters (R. Schreier and G.C. Temes) (Piscataway, NJ: IEEE Press/Wiley, 2005). He also wrote approximately 300 papers in engineering journals and conference proceedings. Dr. Temes was an Associate Editor of the Journal of the Franklin Institute, Editor of the IEEE TRANSACTIONS ON CIRCUIT THEORY, and Vice President of the IEEE Circuits and Systems (CAS) Society. In 1968 and in 1981, he was cowinner of the IEEE CAS Darlington Award, and in 1984, winner of the Centennial Medal of the IEEE. He received the Andrew Chi Prize Award of the IEEE Instrumentation and Measurement Society in 1985, the Education Award of the IEEE CAS Society in 1987, and the Technical Achievement Award of the IEEE CAS Society in 1989. He received the IEEE Graduate Teaching Award in 1998, and the IEEE Millennium Medal, as well as the IEEE CAS Golden Jubilee Medal in 2000.

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